Magnetoresistive random access memory (MRAM) devices with magnetic tunnel junctions (MTJs) have shown desirable characteristics that are believed to be advantageous over conventional non-volatile memory and random access memory (RAM) technologies. The dimensions of MRAM elements are progressively scaled down to increase the densities of MRAM devices for larger scale integration. Attempts have been made to fabricate MRAM devices with advanced semiconductor processing technologies for smaller nodes, for example, for 40 nm nodes or below. However, as the size of an MRAM device is scaled down making an electrical contact to the top electrode of an MTJ becomes increasingly difficult due to the scaling down of the vertical height of the interconnect via and the intrinsic etch profile of MRAM device and the critical dimension (CD) of the MTJ.
Various solutions have been proposed for making top electrical contacts to MTJs in MRAM devices in advanced process nodes. For example, a critical planarization step using a conventional planarization process, such as a chemical mechanical planarization (CMP) process, has been proposed to expose the top electrodes of the MTJs. However, the final MTJ metal hard mask height will be limited by the tolerance of the CMP process step, which degrades yield and is not suitable for advanced process nodes, such as the 28 nm node.
Other techniques that have been proposed for forming top electrical contacts to MTJs with relatively large dimensions include using special vias or landing a subsequent back-end-of-line (BEOL) interconnect level on the MTJs. However, these techniques are typically not practical in advanced process nodes that are 40 nm or below.